Experimental demonstration of components for neuromorphic accelerator Domain Walls
The non-volatility and low energy consumption of spintronic and magnetic devices are advantageous in implementations of neural networks. In this work, we demonstrate that the application of non‑volatile technologies to linear operations such as matrix convolution can be supplemented by the ability of spintronics to compute nonlinear functions such as thresholding.
Using optical and electronic characterization, we demonstrate that three terminal magnetic tunnel junctions (component for high-density magnetic memory) can be designed to implement arbitrary monotonic nonlinear functions. For application to linear operations, devices are built with multiple tunnel junctions on wires with linearly varying width along their length. In contrast, nonlinear operations can be performed by fabricating devices with varying widths such that the current density and hence the spin-orbit torque is a nonlinear function of the domain wall position. Our synaptic devices can overcome the two critical issues – linearity and asymmetry, and our thresholding devices can increase the parallelism of convolution operation.
Publication: S. Siddiqui et al., Magnetic Domain based Synaptic and Activation Function Generator for Neuromorphic Accelerators, Nano Lett. 20, 2, 1033 (2020).
Design of magnetic tunnel junction for convolutional neural network
By micromagnetic and electrical simulations, we have demonstrated that the magnetic tunnel junction can be engineered to use as a weight generator and activation function generator for neuromorphic hardware. We showed that magnetic tunnel junctions based on spin-orbit torque offer a pathway to low-power resistive analog circuits. This technology is compatible with conventional complementary metal-oxide-semiconductor (CMOS) circuits in electrical design and in process technology. Our system level simulation shows that combining the analog MTJ synapses and function generators with 45-nm CMOS provides significant speedup for deep convolutional neural network.
Publication: S. Dutta, S. Siddiqui et al., IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2017.