Research Highlights
SYNTHESIZE HARDWARE WITHOUT HARDWARE EXPERTISE
Researchers at the Advanced Digital Sciences Center (ADSC) have obtained notable success in enabling software engineers to produce hardware designs with the quality expected of experienced hardware designers, but with the fast design cycle of high-level languages and little to no need for hardware design expertise. To date, ADSC researchers have demonstrated the generation of good-quality FPGA hardware designs from high-level C-like code intended for GPU programming, with minimal hints from the programmer to guide the design process. The resulting reduction of hardware design time from months down to minutes will radically enhance a software team’s ability to innovate rapidly and make iterative improvements to algorithms.
Users of prior high-level synthesis (HLS) tools must have significant hardware expertise and expend considerable effort to annotate and transform code before HLS, which typically requires specialized languages as input. In contrast, ADSC targets situations in which a software engineer with little or no understanding of hardware design wants to implement an algorithm in hardware to accelerate performance. In such situations, the target platform will be heterogeneous, combining one or more CPUs, graphical processing units (GPUs), and/or field-programmable gate arrays (FPGAs). ADSC’s HLS approach, calledFCUDA, takes the C-based GPU programming language CUDA as input and produces FPGA or GPU designs, thus allowing software engineers to use a single familiar language to program all parts of their platform. Thus FCUDA provides engineering teams with a midpoint in performance between a pure software implementation and a manual FPGA hardware implementation, but with little to no additional design effort or design time to generate the hardware.
FCUDA’s FPGA hardware designs achieve performance on par with their GPU counterparts, but consume 90% less power. Further, ADSC has eliminated over 75% of the manual annotations on CUDA input that would ordinarily be needed for the FPGA design, and is in the process of removing all others except those describing the FPGA’s user interface. The research community has recognized the importance of this work with two best paper prizes, and ADSC’s audiovisual researchers now use FCUDA to quickly synthesize hardware for their digital signal processing algorithms, which are a vital ingredient in ADSC’s broader research program to provide low-cost, high-quality, real-time immersive telepresence.
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