I am a first year Ph.D. student at the University of Illinois, Urbana-Champaign, and my research advisor is Prof. Sarita Adve.
My primary research interest is computer architecture. However, I am also interested in topics across the computing stack — from systems to devices.
Before starting my Ph.D., I worked at Intel Corporation as part of the IoT group. During my time at Intel, I have worked on pre-silicon and post-silicon validation, and power and performance evaluation. I have been a part of the 4G/5G modem projects and later, the Movidius VPU hardware accelerators.
Before Intel, I received my B. Tech. in Electronics and Communication Engineering from Vellore Institute of Technology in 2017.
I am currently working on the Spandex project. As part of our current research, we ask the high-level question: how must we redesign our memory hierarchy for modern heterogeneous systems?
More specially, how do we optimize our cache coherence protocols, as we move away from the CPU-centric view of computing? As more of the computation is offloaded to coarse and fine grained accelerators, how do we optimize our data movement — in the process, reduce off-chip traffic and accelerator invocation overheads?
To answer these questions, we are currently evaluating a hardware implementation of the Spandex coherence protocol (including optimizations from FCS). The latest release of our caches have been integrated with ESP — the open-source research platform for heterogeneous SoC’s from Columbia University. We are leveraging the rich ecosystem of accelerators in a heterogeneous infrastructure offered by ESP to conduct our research.