I am a PhD candidate at the University of Illinois Urbana-Champaign. I am advised by Prof. Sarita Adve and I work on topics in computer architecture and systems.
In our recent work, Mozart, we propose a novel SoC architecture that rethinks control and data interfaces for hardware accelerators. Specifically, Mozart showed that shared memory is general and performant interface for integrating hardware accelerators, and novel capabilities such as fine-grained acceleration, composable accelerators and efficient accelerator pipelining.
I enjoy hardware design and prototyping. In earlier work, I helped realize the benefits of the novel Spandex coherence protocol in synthesizable hardware.
Before starting my PhD, I worked at Intel, as part of the IoT group. My roles included design validation, and power and performance evaluation for IoT products like 5G modems and machine learning accelerators.
Before Intel, I received my B.Tech. in Electronics and Communication Engineering from Vellore Institute of Technology in 2017.
Reach me at vv15@illinois.edu. My CV is here.