University of Illinois at Urbana Champaign
Radha is a doctoral candidate in Computer Science at the University of Illinois at Urbana-Champaign. Her research interests lie, broadly, in the area of Computer Architecture with a specific focus on Approximate Computing, Hardware/Software Resiliency, Error-Efficient Computing and Software Testing. Radha’s dissertation work aims to formalize techniques and build tools that enable reliable, low-cost and efficient computing by allowing controlled errors in the system. Radha’s research work has been published in the top Computer Architecture and Dependability conferences (ISCA, MICRO, ASPLOS, DSN). She was among 20 people invited to participate in an exploratory workshop on error-efficient computing systems initiated by the Swiss National Science Foundation and is one of the select young researchers worldwide to attend the 2018 Heidelberg Laureate Forum.
Before joining the University of Illinois, Radha was a CPU/Silicon validation engineer at Intel where her work won a divisional award for key contributions in validating new industry standard CPU features. Prior to that, she worked briefly at Qualcomm on architectural verification of the Snapdragon processor. Radha has a Master’s in Computer Engineering from North Carolina State University and a Bachelor’s in Electrical Engineering from the University of Madras in India.
The end of conventional technology scaling has led to notable interest in techniques such as approximate computing and ultra-low cost resiliency solutions that aim to improve the overall efficiency of the system by allowing it to make controlled errors (deliberate approximations or unintentional hardware errors). Such systems can be considered error-efficient: they only prevent as many errors as they need to. Error-efficient computing paradigms have the potential to significantly change the way we design hardware and software (current systems are designed for exact computations). However, their widespread adoption depends on developing a fundamental and precise understanding of how errors in computation and data affect the output of a given program (referred to as the program’s error profile). Today, we rely on program/domain experts to articulate and quantify the error profile of (select) applications which severely limits the scope and promise of emerging error-efficiency techniques.
My research furthers the state-of-the-art in error-efficient computing in three broad ways: (1) by developing efficient and automatic tools to extract comprehensive and accurate instruction and data error profiles of general-purpose applications, thereby limiting programmer input to only high-level domain-specific information, (2) by exploiting application error profiles to enable efficiencies through approximate computing and ultra-low cost hardware resiliency while providing quality-of-service guarantees to the end-user and (3) by improving fundamental understanding of how applications/systems behave when perturbed by errors.