HPC Performance Architect
Huda Ibeid is an HPC Performance Architect at Intel. Prior to that, she was a postdoctoral researcher at the University of Illinois at Urbana-Champaign. She holds a PhD in Computer Science from King Abdullah University of Science and Technology (KAUST). Her research interests are broadly in the area of high-performance computing, with a focus on two topics: the development of performance models for parallel architectures and applications, and the development of scalable numerical algorithms for partial differential equations (PDEs). She is the recipient of the Google Women Techmakers Scholarship.
Exascale systems are predicted to have approximately one billion cores, assuming gigahertz cores. Limitations on affordable network topologies for distributed memory systems of such massive scale bring new challenges to the currently dominant parallel programming model. It is therefore of interest to model applications performance to understand what changes need to be made to ensure extrapolated scalability. Among the scientific applications ripe for reconsideration, those governed by elliptic PDEs will be among the most challenging. Although many successful numerical methods for such PDEs exist, changing computer architectures necessitate new paradigms for computing and the development of new algorithms. Computer architectures of the future will favor algorithms with high concurrency, high arithmetic intensity, and low synchronicity. Since the processor frequency has plateaued, Moore’s law holds continued promise only for those who are willing to make algorithmic changes.