Electronic design automation must evolve in response to increasingly ambitious goals for low power and high performance, which are accompanied by a decreasing design cycle time. There is an unmet need for models, methods and tools that enable fast and accurate design and verification while protecting intellectual property. A behavioral approach to systems modeling will meet these objectives. CAEML will pioneer the application of emerging machine-learning techniques to microelectronics and micro-systems modeling. Existing methods fall short when applied to systems with many ports, which contain reliability hazards, have non-linear responses, and have variability. This are addressing this problem jointly with our microelectronics industry partners whose diverse products include electronic design automation tools, integrated circuits, mobile systems, and test equipment. Close engagement with these industry partners ensures that the Center provides models and tools that will facilitate communications between customers and suppliers across the entire industry value chain while protecting the proprietary information of all parties. This leads to more efficient and reliable production, and better yields.
CAEML is developing new domain-specific machine learning algorithms to extract models using limited training data. Designers’ prior knowledge is utilized to speed-up learning and to impose physical constraints on the models.
Research Projects for 2018:
|Modular Machine Learning for Behavioral Modeling of Microelectronic Circuits and Systems|
Modern machine learning algorithms are inherently modular. This modularity, combined with the behavioral approach to system design and simulation, will be leveraged to develop mathematical tools for assessing the performance and minimal data requirements for learning a low-complexity representation of the system behavior, one component or subsystem at a time.
|Intellectual Property Reuse Through Machine Learning
Recast an analog or full custom digital design from one technology node to another, assuming the same circuit topology.
|Behavioral Model Development for High-Speed Links|
Systematically develop a hierarchy of behavioral models of circuits that protects IP, has the same accuracy as the transistor-level models, but require 25–50X less CPU time and memory.
|Models to Enable System-level Electrostatic Discharge Analysis
ML is used to create ESD models of the system’s nonlinear components, as needed for SOA analysis and soft failure prediction. The models are targeted for circuit or mixed-mode (EM-circuit) simulators.
|Optimization of Power Delivery Networks for Maximizing Signal Integrity|
Develop ML based methods to optimize the system output response based on a large set of design (control) parameters. Co-optimization of the signal path and power delivery network under a multi-physics environment to maximize performance.
|Machine Learning for Trusted Platform Design
Use ML techniques to assess if an IoT system is under cyber attack via power or RF side-channels and develop hardware countermeasures to identify and nullify such attacks.
|Machine Learning to Predict Successful FPGA Compilation Strategy|
Produce FPGA compilation recipes that show high success rate and fast compilation time.
|Causal Inference for Early Detection of Hardware Failure
Use time-series sensor data to detect wear-out of a hardware component, e.g. HDD or SSD in a storage array. Longitudinal causal inference techniques will omit redundant covariates or features that might be correlated with the failure but do not help in the prediction task.
|Applying Machine Learning to Back End IC Design|
Back end design refers to physical design of an ASIC, including place and route. The goal of this project is to use machine learning to set up the physical design tools on a design by design basis so that optimum results can be achieved with minimal human interaction.
This material is based on work supported by the National Science Foundation under Grant Number CNS 16-24811.