Electronic design automation must evolve in response to increasingly ambitious goals for low power and high performance, which are accompanied by a decreasing design cycle time. There is an unmet need for models, methods and tools that enable fast and accurate design and verification while protecting intellectual property. A behavioral approach to systems modeling will meet these objectives. CAEML will pioneer the application of emerging machine-learning techniques to microelectronics and micro-systems modeling. Existing methods fall short when applied to systems with many ports, which contain reliability hazards, have non-linear responses, and have variability. This are addressing this problem jointly with our microelectronics industry partners whose diverse products include electronic design automation tools, integrated circuits, mobile systems, and test equipment. Close engagement with these industry partners ensures that the Center provides models and tools that will facilitate communications between customers and suppliers across the entire industry value chain while protecting the proprietary information of all parties. This leads to more efficient and reliable production, and better yields.
CAEML is developing new domain-specific machine learning algorithms to extract models using limited training data. Designers’ prior knowledge is utilized to speed-up learning and to impose physical constraints on the models.
Research Projects for Spring 2017:
|Modular Machine Learning for Behavioral Modeling of Microelectronic Circuits and Systems|
This project focuses on theoretical foundations and modular algorithmic solutions for ML-driven design, simulation, and verification of high-complexity, multifunctional electronic systems. Behavioral system modeling provides a systematic approach to reconciling the variety of physics-based and simulation-based models, expert knowledge, and other possible means of component description commonly introduced in electronic systems modeling. In complex electronic systems, each component model comes with its own sources of errors, uncertainty, and variability, and the same applies to the way components and subsystems are connected and interact with each other in the integrated system. The modularity offered by the behavioral approach will be leveraged to develop mathematical tools for assessing the performance and minimal data requirements for learning a low-complexity representation of the system behavior, one component or subsystem at a time, from measured and simulated data, even in highly complex and uncertain settings. We will develop and implement the full ML algorithmic pipeline and quantify its end-to-end performance in applications pertinent to multifunctional electronic system design, simulation, and verification.
|Behavioral Model Development for High-Speed Links
High-speed links consist of driver and receiver circuits connected to each other through interconnections in the chip, package, and printed circuit board. Over several decades, as the speed of the channel has increased, the driver and receiver circuits have become quite complex to compensate for any shortcomings of the channel; e.g., they contain pre-distortion, pre-emphasis, adaptive control, and equalization circuitry. This project’s goal is to apply machine-learning methods to systematically develop a hierarchy of behavioral models of the driver/receiver circuits that have the same accuracy as the transistor-level models, but require 25–50X less CPU time and memory. The behavioral models will be suitably parameterized to include a range of channel conditions that can be used for design verification and optimization. We will use three approaches for developing the behavioral models: 1) using time domain data obtained directly from the transistor-level models, 2) using X-parameters of the transistor-level circuits, and 3) building receiver models using system identification and surrogate modeling. We will compare the three approaches as part of this project.
|Design Rule Checking with Deep Networks|
In this seed project, we will investigate the feasibility of training a deep convolutional network to perform Design Rule Checking (DRC). By replacing DRC with a recognition network, we hope to greatly speed it up. After showing initial feasibility, in following years, we will investigate tying DRC to interactive layout tools.
|Intellectual Property Reuse Through Machine Learning
Demonstrate a tool ﬂow that will permit IP blocks to be migrated from one technology node to another and re-optimized for the new technology and application. This is a constrained optimization problem that is suitably addressed using goal programming techniques. High Dimensional Model Representation (HDMR) approaches will be developed to manage the large number of design dimensions.
|Optimization of Power Delivery Networks for Maximizing Signal Integrity|
Power distribution is a system-level problem in which the contributions from the chip, package, and printed circuit board are equally important. This, when combined with signal lines, can lead to models that can take a long time to simulate. With optimization being an integral part of design, co-optimization of the signal and power delivery network becomes necessary. As the number of control parameters increases, this co-optimization process can be very time-consuming. The objective of this project is to explore and develop machine learning (ML) based software to optimize the output response of the system based on a large set of input (or control) parameters. The focus is on using expert ML methods that allow for fast convergence with little data (rather than big data). We will focus on two key applications as part of this project: 1) DDR4 and other emerging memory channels where the speed is being increased beyond 3 GHz, the voltage is being scaled below 1.2 V, and timing margins less than 100 ps are required; and 2) High Bandwidth Memory (HBM) integrated in close proximity to the processor through use of 3D technology, where temperature gradients on the PDN affect signal integrity.
|Models to Enable System-level Electrostatic Discharge Analysis
This project seeks to develop accurate but computationally efficient models so that simulation may be used to assess the ESD response of different combinations of integrated circuits, on-board protection elements, and circuit board designs. Simulation will be used to predict if any component within the system will be driven outside its safe operating area or whether there is a high likelihood of soft failures. A system identification approach will be used to learn the model from data. Acquisition of suitable training data for ESD model learning requires significant time and expertise; therefore, active learning will be exploited to minimize the amount of training data needed and focus the data collection on regions of the input space that are most relevant to ESD conditions. The behavioral model used to represent an IC pin’s transient voltage response to an incoming ESD current pulse will contain multiple ports to account for the multiple return paths among the many supply and ground pins and the influence of the board-level power delivery network (PDN) on the pin’s I-V characteristic. Stability of the on-chip power supply is similarly affected by the board-level PDN and has a major impact on the occurrence of soft failures. Behavioral models of the on-chip supply that extend to ESD current/voltage levels (where the power supply clamps are activated) will be developed. Methods to obtain a probabilistic description of the ESD soft failure occurrence will be investigated.