Workshop on Machine Learning for Hardware Design

New event! 1 PM – 4 PM, Wednesday October 18, on-site at the San Jose Doubletree Hotel following EPEPS.

Workshop on Hardware Design using Machine Learning. No charge to attend. Advanced registration requested: REGISTRATION

Learn how industry and academia are successfully applying statistical learning theory and machine learning algorithms to advance the state-of-the-art in electronic design automation, with emphasis on Signal Integrity, Power Integrity, and Advanced IC and Packaging Technologies. Statistical modeling techniques such as Bayesian inference, surrogate modeling, and generative modeling are used to accelerate design in a variety of application spaces, including high-speed links, power distribution, system-level ESD, IP reuse,  and place and route. The workshop speakers are affiliated with the NSF-sponsored Center for Advanced Electronics through Machine Learning. Tentatively scheduled university speakers include Elyse Rosenbaum (UIUC), Paul Franzon (NCSU), Madhavan Swaminathan (Georgia Tech) and industry speakers from Cadence, HPE, IBM, and Qualcomm.

For more information about CAEML, visit