Workshop on Machine Learning for Hardware Design

New event! 1 PM – 4 PM, Wednesday October 18, on-site at the San Jose Doubletree Hotel following EPEPS.

Workshop on Hardware Design using Machine Learning. No charge to attend.

Advance registration requested.

Learn how industry and academia are successfully applying statistical learning theory and machine learning algorithms to advance the state-of-the-art in electronic design automation, with emphasis on Signal Integrity, Power Integrity, and Advanced IC and Packaging Technologies. Statistical modeling techniques such as Bayesian inference, surrogate modeling, and generative modeling are used to accelerate design in a variety of application spaces, including high-speed links, power distribution, system-level ESD, IP reuse,  and place and route. The workshop speakers are affiliated with the NSF-sponsored Center for Advanced Electronics through Machine Learning.

CAEML Workshop Agenda           Workshop Bios

Scheduled university speakers:

Workshop Introduction

Elyse Rosenbaum (Illinois) Predictive Simulation of ESD-induced Failures in Microelectronic Systems

Paul Franzon (NCSU) Machine Learning for Next Generation EDA

Madhavan Swaminathan (Georgia Tech) Machine Learning and its Application to Integrated Systems

Jose Schutt-Aine (Illinois) Machine Learning with X Parameters for Behavioral Model Synthesis

Scheduled Industry speakers:

An-Yu Kuo (Cadence) System Level ESD Simulation with Machine Learning

Chris Cheng (HPE) Machine Learning in System Design

Dale Becker (IBM) Machine Learning for High-Speed Channel Design

Tim Michalka (Qualcomm) Machine Learning for Selected SI & PI Problems


For more information about CAEML, visit