Earlier work in CAEML (“Applying Machine Learning to Back End IC Design”) will be used to generate models of performance, area and static power. This project focuses on the important missing piece—dynamic power prediction. Parameterized RTL source code and a test-bench with embedded architectural event counters must be provided for each circuit block. This work seeks to eliminate the complicated gate-level simulations presently needed to make accurate predictions of power, which typically occur very late in the design process. This project will develop a comprehensive data mining methodology to maximize the accuracy of PPA predictions while minimizing the data collection effort. A central challenge of this project is to show that high-level events are meaningful predictors of dynamic power.

Project PIs: Rhett Davis, Paul Franzon, Dror Baron, Eric Rotenberg

Research Thrust: Design and System Optimization

Research Timeline Jan 1, 2019 – Dec 31, 2020