Designing advanced semiconductor manufacturing process brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Often times there are post tape-out escapes both at the silicon and packaging levels due to inadequate analysis at an early design stage. This sometimes is due to lack of time or poor assumptions made by the designer which may be inaccurate. We address these challenges in this project by focusing on early Design Space Exploration (DSE). Such a solution we believe would be applicable to various levels in the system hierarchy.
Research Thrust: Design and System Optimization; Reliability and Security
Research Timeline Jan 1, 2019 – Dec 31, 2020