Current Research Projects

Applying Machine Learning to Back End IC Design

Back end design refers to physical design of an ASIC, including place and route. The goal of this project is to use machine learning to set up the physical design tools on a design by design basis so that optimum results can be achieved with minimal human interaction.

Project PIs: Rhett Davis, Paul Franzon, Dror Baron

Research Thrust: Design and System Optimization; Verification

Research Timeline Jan 1, 2018 – Dec 31, 2020

NL2PPA: Netlist‐to‐PPA Prediction Using Machine Learning

This project aims to build machine learning models and develop associated tools to predict PPA (power/performance/area) given an RTL description of a circuit, eliminating the need to undertake the lengthy physical design process. Using the predicted PPA results, designers can fix and/or improve RTL in turn. The inputs to the model include the target technology specs (e.g., technology node, supply voltage, target frequency), netlist info (e.g., number of IPs/gates/nets, connectivity), physical design options (e.g., footprint, placement density, P&R algorithms, clock/power network options), and other key features that will help improve the prediction accuracy.

Project PI: Sungkyu Lim

Research Thrust: Design and System Optimization

Research timeline: January 1, 2019 – December 31, 2020

RNN Models for Computationally‐Efficient Simulation of Circuit Aging Including Stochastic Effects

This project will develop a method for accurate and efficient simulation of circuit aging due to hot carrier injection (HCI) and bias temperature instability (BTI). For design-technology co-optimization (DTCO), the simulations must cover the range of use conditions, i.e., the “mission profile,” which includes the input vector, and both the deterministic and stochastic aspects of aging should be simulated. Each circuit block, i.e. library cell or IP block, will be represented by a limited-complexity black-box model, such as the RNN, that takes the circuit’s total operating time as one of its inputs. Ensuring the stability of each black-box model alone and when interconnected to other circuit models is a significant research challenge.

Project PIs:  Elyse Rosenbaum, Maxim Raginsky

Research Thrust: Modeling and Simulation; Reliability and Security

Research Timeline: January 1, 2019 to December 31, 2020

High-Speed Bus Physical Design Analysis through Machine Learning

This project will create a dynamic ML ecosystem to characterize electrical performance of each net in a given PCB/package layout file with confidence bounds and leverage pre-PD simulation to collect training data. The use of stochastic collocation to will be used to account for manufacturing tolerance and nets will be ranked in descending order of SI performance to determine any bottleneck in the system.

Project PIs: Xu Chen, Madhavan Swaminathan

Research Thrust: Design and System Optimization; Modeling and Simulation; Verification

Research Timeline Jan 1, 2019 – Dec 31, 2020

Enabling Side‐Channel Attacks on Post‐Quantum Protocols through Machine Learning

The primary purpose of this project is to enable single-trace power side-channel attacks on post-quantum key-exchange protocols using machine learning and to quantify the strength of timing obfuscation defenses against those attacks. The central question to be addressed is whether machine-learning classifiers provide stronger attacks compared to the conventional ones in the context of post-quantum cryptosystems, and to what extent can obfuscation methods hide the vulnerability.

Project PI: Aydin Aysu

Research Thrust: Reliability and Security

Research Timeline Jan 1, 2019 – Dec 31, 2020

Design Space Exploration Using DNN

Designing advanced semiconductor manufacturing process brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Often times there are post tape-out escapes both at the silicon and packaging levels due to inadequate analysis at an early design stage. This sometimes is due to lack of time or poor assumptions made by the designer which may be inaccurate. We address these challenges in this project by focusing on early Design Space Exploration (DSE). Such a solution we believe would be applicable to various levels in the system hierarchy.

Project PI: Madhavan Swaminathan

Research Thrust: Design and System Optimization; Reliability and Security

Research Timeline Jan 1, 2019 – Dec 31, 2020

FPGA Hardware Accelerator for Real Time Security

Determine design approaches to building real time detection systems for ransomware defenses, with a focus on Random Forest ML.  Investigate the training support needs as well.  Determine higher level ML approaches that support model update without redesign.

Project PI: Paul Franzon

Project Timeline: Jan 1, 2020 – Dec 31, 2021