Modular Machine Learning for Behavioral Modeling of Microelectronic Circuits and Systems
Modern machine learning algorithms are inherently modular. This modularity, combined with the behavioral approach to system design and simulation, will be leveraged to develop mathematical tools for assessing the performance and minimal data requirements for learning a low-complexity representation of the system behavior, one component or subsystem at a time.
Project PIs: Maxim Raginsky, Andreas Cangellaris
Project Research Thrust: Theory and Machine Learning Efficiency
Research Timeline Jan 1, 2017 – May 16, 2020
Intellectual Property Reuse through Machine Learning
The objective of this project was to demonstrate that machine learning can be applied to the problem of recasting an analog or full custom digital design from one technology node to another, assuming the same circuit topology.
Project PIs: Paul Franzon, Brian Floyd
Research Thrust: Design and System Optimization
Research Timeline Jan 1, 2017 – Dec 31, 2018
Design Rule Checking with Deep Networks
In this seed project, we investigated the feasibility of training a deep convolutional network to perform Design Rule Checking (DRC). By replacing DRC with a recognition network, we hope to greatly speed it up. After showing initial feasibility, in following years, we investigated tying DRC to interactive layout tools.
Project PIs: Paul Franzon, Rhett Davis
Research Thrust: Verification
Research Timeline Jan 1, 2017 – Dec 31, 2017
Behavioral Model Development for High-Speed Links
Systematically develop a hierarchy of behavioral models of circuits that protects IP, has the same accuracy as the transistor-level models, but require 25–50X less CPU time and memory.
Project PIs: Madhavan Swaminathan, Paul Franzon, Jose Schutt-Aine
Research Thrust: Modeling and Simulation; Design and System Optimization
Research Timeline Jan 1, 2017 – Aug 15, 2020
Models to Enable System-level Electrostatic Discharge Analysis
ML is used to create ESD models of the system’s nonlinear components, as needed for SOA analysis and soft failure prediction. The models are targeted for circuit or mixed-mode (EM-circuit) simulators.
Project PIs: Elyse Rosenbaum, Maxim Raginsky
Research Thrust: Reliability and Security
Research Timeline Jan 1, 2017 to May 31, 2019
Optimization of Power Delivery Networks for Maximizing Signal Integrity
Develop ML based methods to optimize the system output response based on a large set of design (control) parameters. Co-optimization of the signal path and power delivery network under a multi-physics environment to maximize performance.
Project PI’s: Madhavan Swaminathan, Chuanyi Ji
Research Thrust: Design and System Optimization
Research Timeline Jan 1, 2017 – Dec 31, 2018
Machine Learning for Trusted Platform Design
Use ML techniques to assess if an IoT system is under cyber attack via power or RF side-channels and develop hardware countermeasures to identify and nullify such attacks.
Project PIs: Arijit Raychowdhury, Madhavan Swaminathan
Research Thrust: Reliability and Security
Research Timeline Jan 1, 2018 – May 7, 2020
Machine Learning to Predict Successful FPGA Compilation Strategy
Produce FPGA compilation recipes that show high success rate and fast compilation time.
Project PIs: Sungkyu Lim
Research Thrust: Design and System Optimization; Verification
Research Timeline Jan 1, 2018 – Dec 31, 2019
Causal Inference for Early Detection of Hardware Failure
Use time-series sensor data to detect wear-out of a hardware component, e.g. HDD or SSD in a storage array. Longitudinal causal inference techniques will omit redundant covariates or features that might be correlated with the failure but do not help in the prediction task.
Project PIs: Negar Kiyavash, Maxim Raginsky, Elyse Rosenbaum
Research Thrust: Theory and Machine Learning Efficiency
Research Timeline Jan 1, 2018 – May 31, 2019
Fast, Accurate PPA Model‐Extraction
Earlier work in CAEML (“Applying Machine Learning to Back End IC Design”) will be used to generate models of performance, area and static power. This project focuses on the important missing piece—dynamic power prediction. Parameterized RTL source code and a test-bench with embedded architectural event counters must be provided for each circuit block. This work seeks to eliminate the complicated gate-level simulations presently needed to make accurate predictions of power, which typically occur very late in the design process. This project will develop a comprehensive data mining methodology to maximize the accuracy of PPA predictions while minimizing the data collection effort. A central challenge of this project is to show that high-level events are meaningful predictors of dynamic power.
Project PIs: Rhett Davis, Paul Franzon, Dror Baron, Eric Rotenberg
Research Thrust: Design and System Optimization
Research Timeline Jan 1, 2019 – May 7, 2020
High-Dimensional Structural Inference for Non-Linear Deep Markov or State Space Time Series Models
In many applications, a time series of high-dimensional latent vector variables is observed indirectly from noisy measurements. The data are used to predict future failures, and the system can respond accordingly. This project will investigate deep Markov models (DMMs), in which an inference network approximates a posterior probability for the time-dynamics of latent variables by running a multi-layer perceptron (MLP) neural network. We will implement and develop a DMM system that can cope with various types of statistical structure among the features, and pay close attention to scaling the computation as the dimensionality increases.
Project PIs: Dror Baron, Rhett Davis, Paul Franzon
Research Thrust: Theory and Machine Learning Efficiency
Research Timeline Jan 1, 2019 – May 7, 2020