Behavioral Model Development for High-Speed Links

Systematically develop a hierarchy of behavioral models of circuits that protects IP, has the same accuracy as the transistor-level models, but require 25–50X less CPU time and memory.

Project PIs: Madhavan Swaminathan, Paul Franzon, Jose Schutt-Aine

Research Thrust: Modeling and Simulation; Design and System Optimization

Research Timeline Jan 1, 2017 – Dec 31, 2018