CAEML research update

Elyse Rosenbaum
Elyse Rosenbaum

Now in its third year of existence, the Center for Advance Electronics through Machine Learning (CAEML) is funding 11 research projects. Four of those grants are renewals, and seven are for new projects.

Asked about the new projects, Center Director Elyse Rosenbaum made the following remarks.

“The new research projects leverage the early work done by the center’s researchers. For example, in the initial set of projects, we developed optimization techniques that are especially well suited for electronic system design and identified behavioral model classes that can be used to represent a wide variety of integrated circuits. In the center’s current research portfolio, there is an increasing focus on security applications and on design planning, e.g., PPA (power-performance-area prediction) and DTCO (design-technology co-optimization.”

The principal investigators (PI) of the projects are spread out among CAEML’s three partner institutions, the University of Illinois at Urbana-Champaign, North Carolina State University (NCSU) and the Georgia Institute of Technology. The membership fees paid by the center’s twelve industry partners provide the research funds. Each industry member has a representative on the board that votes on which projects to support. The industry partners joined CAEML for the opportunity to develop relationships with graduate students, options for licensing or intellectual property acquisition, and to see what might be next for the industry.

The new projects for 2019 are as follows:

  • Netlist-to-PPA Prediction Using Machine Learning, PI Sung Kyu Lim of Georgia Tech, two-year project

This project aims to build machine learning models and develop associated tools to predict PPA (power/performance/area) given an RTL description of a circuit, eliminating the need to undertake the lengthy physical design process.

  • Fast, Accurate PPA Model-Extraction, PI Rhett Davis of NCSU, two-year project

This project will develop a comprehensive data mining methodology to maximize the accuracy of PPA predictions while minimizing the data collection effort. A central challenge of this project is to show that high-level events are meaningful predictors of dynamic power.

  • RNN Models for Computationally-Efficient Simulation of Circuit Aging Including Stochastic Effects, PI Elyse Rosenbaum of Illinois, two-year project

This project will develop a method for accurate and efficient simulation of circuit aging due to hot carrier injection (HCI) and bias temperature instability (BTI).

  • High-dimensional Structural Inference for Non-linear Deep Markov or State Space Time Series Models, PI Dror Baron of NCSU, one-year project

This project will investigate deep Markov models (DMMs), in which an inference network approximates a posterior probability for the time-dynamics of latent variables by running a multi-layer perceptron (MLP) neural network.

  • High-Speed Bus Physical Design Analysis through Machine Learning, PI Xu Chen, Illinois, and Madhavan Swaminathan, Georgia Tech, two-year project

This project will create a dynamic ML ecosystem to characterize electrical performance of each net in a given PCB/package layout file with confidence bounds and leverage pre-PD simulation to collect training data. The use of stochastic collocation to will be used to account for manufacturing tolerance and nets will be ranked in descending order of SI performance to determine any bottleneck in the system.

  • Design Space Exploration using DNN, PI Madhavan Swaminathan of Georgia Tech, two-year project

Too often, there are post tape-out escapes both at the silicon and packaging levels. This sometimes is due to lack of time or poor assumptions made by the designer. This project seeks to address those challenges by focusing on early Design Space Exploration (DSE). Such a solution should be applicable to various levels in the system hierarchy.

  • Enabling Side-Channel Attacks on Post-Quantum Protocols through Machine-Learning Classifiers, PI Aydin Aysu of NCSU, two-year project

The primary purpose of this project is to enable single-trace power side-channel attacks on post-quantum key-exchange protocols using machine learning and to quantify the strength of timing obfuscation defenses against those attacks. The central question to be addressed is whether machine-learning classifiers provide stronger attacks compared to the conventional ones in the context of post-quantum cryptosystems, and to what extent can obfuscation methods hide the vulnerability.

The selected projects are consistent with CAEML’s stated mission “to enable fast, accurate design and verification of microelectronic circuits and systems by creating machine learning algorithms to derive models used for electronic design automation.“ By speeding up the design and verification of microelectronic circuits and systems, CAEML will reduce development cost and time-to-market for manufacturers of microelectronic products. The center further seeks to eliminate the computational hurdles that often make simulation-based design optimization infeasible, thereby allowing engineers to produce better designs without compromising time-to-market, where a better design may be lower power, more reliable, more secure, and/or lower cost.